This invention relates to methods of modifying the surface of semiconductor wafers during semiconductor wafer fabrication and fixed abrasive articles used in such surface modification processes. The fixed abrasive articles have an exposed major surface comprising an abrasive composite, or composites, coextensive with a backing. The abrasive composites of fixed abrasive articles comprise abrasive particles dispersed throughout a binder.
Integrated circuits are very small, complex electrical components that have multiple metal interconnect layers coupled to a vast number of electrical elements within a very small unit of area. Each layer of an integrated circuit typically has a specific pattern of metal interconnects responsible for the specific characteristics of a particular integrated circuit. To create these patterns of metal interconnects, manufacturers of integrated circuits typically use a precise multi-step fabrication process, One of the starting materials of integrated circuit manufacture is a semiconductor wafer. Typically, semiconductor wafers undergo processing steps, including deposition, patterning, and etching during the semiconductor wafer fabrication process. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., "Abrasive Machining Of Silicon", published in the Annals of the International Institution for Production Engineering Research, (Volume 39/2/1990), pp. 621-635). In a sequence of manufacturing steps, it is often desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing. The surface modification process typically is a form of polishing wherein the process is able to remove cumulative irregularities from the surface in a quick and efficient manner without damaging functional components during the process.
One specific type of wafer surface modification process utilizes slurries of abrasive particles often in conjunction with chemical additives and resilient pads, to planarize the surface of a wafer at various steps during the fabrication of the device. This combination of surface modifying chemical additives and mechanical processing is broadly referred to as chemical mechanical planarization or CMP. Alternatively, CMW may employ a three-dimensional, textured, fixed abrasive articles. Such abrasive articles typically have a precisely shaped composite array that is coextensive with a backing. These fixed abrasive articles have been described in WO-97/11484 and in copending U.S. Ser. No. 08/694,014 (Bruxvoort), now U.S. Pat. No. 5,958,794, incorporated herein by reference. The methods described within these references employ a three dimensional, textured, fixed abrasive article and a working fluid, which may be substantially free of abrasive particles and is able to modify the semiconductor wafer surface.
Typically, CMP is tailored for efficient removal of a particular material from a semiconductor wafer surface. For example, dielectric materials such as polycrystalline silicon, thermal oxide, doped and undoped oxides are commonly applied to the surface of a semiconductor wafer. For a particular surface material such as silicon dioxide, a CMP process comprising a particular working solution that optimizes silicon dioxide removal may be employed. It is also common for metals, such as tungsten, aluminum, copper, gold, silver, to be deposited onto the surface of a semiconductor wafer and one skilled in the art would choose a specific CMP process for the removal of a particular metal(s) on the wafer surface. Other materials processed using CMP methods include silicon nitride, boron nitride, diamond-like carbon films, polyimides, spin-on polymers, aerogels, refractory oxides and suicides, and ferroelectrics.
A particular CMP process may be assigned a removal rate, usually measured in Angstroms per minute, equivalent to the removal of a portion of a layer from a semiconductor wafer surface in a given time period. A CMP process having a high removal rate is advantageous because there may be a large total number of steps required during the semiconductor wafer fabrication process. By decreasing the length of time it takes to complete some of these steps, manufacturers will be able to increase the rate of integrated circuit manufacture. In addition to a high removal rate, it is desirable that a CMP process uniformly remove material parallel to the surface of the wafer to be modified. Uniform removal of material will avoid leaving some regions unmodified and other regions over-modified with the possible destruction of previously created features of an underlying layer, such as metal interconnects.
It is also preferred that a CMP process have a high removal rate stability. Removal rate stability may be defined as the consistent removal of surface material (usually measured in Angstroms per minute) among the wafers modified by the process. For example, a particular CMP process will have high removal rate stability if the rate of removal of surface from the first wafer modified by the CMP process is nearly identical to the rate of removal of the surface of the tenth or twentieth wafer modified by the process. Removal rate stability is an important consideration because difficulties exist in monitoring the removal of the wafer surface during the modification process while controlling the amount of surface material removed per wafer. A CMP process with a high removal rate stability would ensure that subsequent identical semiconductor wafers modified by the process will have nearly identical amounts of surface material removed and minimize the need for on-line metrology or frequent off-line confirmation of anticipated removal rate.